◆ICPP 2011 Program Guide

◆ICPP 2011 Schedule plan

◆Keynote 1 The Cloud, the Client and Big Data

September 14

Dr. Dennis Gannon is Director of Cloud Research Engagements for the Microsoft  Technical Policy Group.   Dr. Gannon's research interests include cloud computing, data analytics and “ big data” platforms, large-scale cyberinfrastructure, distributed computing, parallel programming, computational science and problem solving environments.   At Microsoft he and his team are working with the research community to demonstrate the potential of cloud computing to enable broad access to data-intensive scientific research.

Prior to coming to Microsoft, Dr. Gannon was a professor and former chair of computer science at Indiana University and the Science Director for the Indiana Pervasive Technology Labs.  He has published over 100 refereed articles and he has co-edited 3 books.  Dr. Gannon received his Ph.D. in Computer Science from the University of Illinois Urbana-Champaign  after receiving a Ph.D. in Mathematics from the University of California, Davis.

Dennis Gannon
Director of Cloud Research Engagements
eXtreme Computing Group
Microsoft Research

Abstract
The first paradigm of science was experimental. This was quickly followed by the second paradigm, theory, to explain the results of experiments. The third paradigm was computation which allows us to explore theory where experimentation is difficult or impossible. There is a fourth paradigm that can be described as deriving new knowledge from massive amounts of data even in cases where we may have very little theory to guide us. This is important because almost every branch of academic research is inundated by the data deluge and basic research methods have to evolve rapidly to cope with it. Access to massive amounts of digital data has already transformed the IT industry. Massive scale data clouds designed to index the web have transformed the advertising and publishing industry. We have mobile client devices that have applications that give us total information about where we are at any given instant including where to eat and where to catch a cab. Our computers are learning to see and recognize us as we walk through instrumented spaces. That capability is the result of machine learning applied to massive data collections. However, the academic research community is lagging behind in this revolution. While the most adventurous researchers have access to massive supercomputing facilities and communities like high energy physics have well established data analysis pipelines, the majority of researchers limit the scope of their research to what they can do with the computer on their desk. In this talk we will discuss an approach to removing this limitation by building cloud-based data analytics services that are easy to use from the researchers desktop.

◆Keynote 2  Execution Models without Borders

September 15

Dr. Thomas Sterling holds the position of Professor of Informatics and Computing at the Indiana University (IU) School of Informatics and Computing as well as serving as Director of the Laboratory for System Science and Engineering at the IU Center for Research in Extreme Scale Technology (CREST). He also is an Adjunct Professor at the Louisiana State University (LSU) Center for Computation and Technology (CCT) and CSRI Fellow at Sandia National Laboratories. Since receiving his Ph.D from MIT in 1984 as a Hertz Fellow he has engaged in applied research in related fields associated with parallel computing system structures, semantics, and operation in industry, government labs, and academia. Dr. Sterling is best known as the "father of Beowulf" for his pioneering research in commodity/Linux cluster computing. He was awarded the Gordon Bell Prize in 1997 with his collaborators for this work. Thomas Sterling currently leads the ParalleX Research Group to devise a new model of computation establishing the foundation principles to guide the co-design for the development of future generation Exascale computing systems by the end of this decade. His research has been sponsored by NSF, NASA, NSA, DOE, DARPA, Army Corps of Engineers, and Microsoft. He is the co-author of six books and holds six patents.

Thomas Sterling
School of Informatics and Computing
and Pervasive Technology Institute
Indiana University
Fellow, Computer Science Research Institute
Sandia National Laboratories

Abstract
Technology trends have forced parallel processing to new architecture structures that stress conventional usage practices beyond effective applications. The bounds on increased clock rates due to power constraints and increased processor complexity due to ILP limitations have forced multi/manycore structures in combination with GPU accelerators as typified by three of the top four MPP systems in the world. Once the Communicating Sequential Process (CSP) execution model as reflected by the MPI programming interface dominated both MPP and commodity cluster systems, now the parallel processing community struggles to find alternative methods to effectively program and manage such heterogeneous parallel systems. Historically, the field of HPC has experienced 5 previous phase changes where technology and the need for new classes or architecture and programming methods to exploit it, the most recent more than two decades ago. The fundamental issue that challenges the international parallel processing community is the new HPC phase change that will push us into the era of nano-scale technology and multi-billion-way parallelism by the end of this decade. Such a paradigm shift is critical and its lack of adoption is already impeding progress in hardware and software system codesign and extreme scale application development. The critical performance factors that must be addressed are the interrelated behavior properties of starvation, latency, overhead, and contention.As in the past, any new execution model must mitigate their effects of performance degradation. Also, like the past vector model, SIMD, and CSP execution models, the future model must be international in its adoption, general in its breadth of application, and a powerful tool across industrial manufacturers and ISV suppliers. Essentially all borders must be crossed by the future generation execution model. This Keynote Address will focus on this challenge that affects every nation, every user community, every computational challenge, and every producer. The ParalleX experimental execution model will be described as a concrete exemplar of one possible new paradigm that serves as a framework to synthesize prior art while incorporating innovation in order to provide a way forward, eliminating borders and empowering future cooperation among peoples, domains, disciplines, and standards.

◆Keynote 3 The "Single-chip Cloud Computer", an IA Tera-scale Research Processor

September 16

Jim Held is an Intel Fellow who leads a virtual team of architects conducting Tera-Scale Computing Research in Intel's Labs. Since joining Intel in 1990, he has led research and development in a variety of Intel's architecture labs concerned with media and interconnect technology, systems software, multi-core processor architecture and virtualization. Before coming to Intel, Jim worked in research and teaching capacities in the Medical School and Department of Computer Science at the University of Minnesota where he earned a Ph.D. (1988) in Computer and Information Science.

Jim Held
Intel Fellow
Director, Tera-Scale Computing Research Intel Labs

Abstract
Intel Labs has created a second generation experimental "Single-chip Cloud Computer," (SCC) that contains the most Intel Architecture cores ever integrated on a silicon CPU chip - 48 cores. SCC is a concept vehicle, incorporating technologies intended to scale multi-core processors to 100 cores and beyond, such as an on-chip network, advanced power management technologies and support for message-passing. Architecturally, SCC is a microcosm of a cloud datacenter. Each core can run a separate OS and software stack and act like an individual compute node that communicates with other compute nodes over the on-die network fabric, thus supporting the "scale-out" message-passing programming models that have been proven to scale to 1000s of processors. The SCC also serves as an experimental platform for a wide range of parallel computing research on scalable programming models and architectures and increasing our understanding of how to build better processors for the Cloud. It is currently being used by a worldwide community of academic and industry co-travelers.
This talk will describe the architecture of the SCC platform and discuss its role in the broader context of our Tera-scale research.

◆Panel 1

Programming Environments at Extreme Scale
Exa-scale systems are expected to present an extremely large challenge to computational scientists attempting to leverage the full extent of the capabilities such systems will provide.  The systems are expected to have on the order of ten million computational elements, with order several-hundred such cores per node, include multiple types of computational elements, and have non-uniform memory access characteristics with deep memory hierarchies.  Applications are also expected to need touse on the order of ten to one-hundred way concurrency per core, provided by fine-grain multithreading.  The challenges for application developers trying to use such systems is to understand in detail how their codes perform on such systems, and how these codes need to be changed to make better use of such systems. This panel will discuss current and future research directions aimed at helping application developers develop applications for such systems, understand the performance of such applications on these systems, and help in transforming these applications to better utilize such systems.

Panelists:
Barbara Chapman, University of Houston
Robert Harrison, Oak Ridge National Laboratory
Richard L. Graham, Oak Ridge National Laboratory
Martin Schulz, Lawrence Livermore National Laboratory
Wolfgang Nagel, The Technical University of Dresden

◆Panel 2

Opportunities and Challenges in Multi-core Era: A Cross-Layer Dialogue
Processors have been moved to multi-core architectures for many years. However, it is still very challenging today to build a scalable, high performance, low-power, and cost-effective multi-core system. The shift towards multi-core not only poses challenges for computer architectures, but also brings news issues distributed across several communities such as applications and algorithms, programming models, languages and compilers, virtual machines, operating systems and run-time supports. This panel gives us an opportunity to stimulate discussions and dialogue across the spectrum of different research communities. We would like to invite researchers from parallel algorithms and applications, programming languages and compiler designs, OSs and run-time supports, and computer architectures to share their ideas from different angle of view, and join our discussion on challenges and research directions of multi-core systems.

Panelists:
Tien-Fu Chen, National Chiao Tung University, Taiwan
Jürg Gutknecht, ETH Zurich, Switzerland
Jim Held, Intel Labs, USA
Chung-Ta King, National Tsing Hua University, Taiwan
Jane Win-Shih Liu, Academia Sinica, Taiwan
Shiao-Li Tsao, National Chiao Tung University, Taiwan

◆Technical Program

• Architecture

• Wireless/Sensor Networks and Pervasive Computing

• Performance and Modeling

• Compilers, Programming Models and Languages

• Cloud Computing

• Cluster and Grid Computing

• Algorithms Design and Parallelization

• Mobile Computing and Networks

• Multi-core and Parallel Systems

• OS and Runtime Technology

• P2P Computing and Services

◆Workshops

• PSTI

• P2S2

• CloudSec

• AWASN

• SRMPDS

• EMS